library verilog;
use verilog.vl_types.all;
entity cmsdk_apb_dualtimers is
    port(
        PCLK            : in     vl_logic;
        PRESETn         : in     vl_logic;
        PENABLE         : in     vl_logic;
        PSEL            : in     vl_logic;
        PADDR           : in     vl_logic_vector(11 downto 2);
        PWRITE          : in     vl_logic;
        PWDATA          : in     vl_logic_vector(31 downto 0);
        TIMCLK          : in     vl_logic;
        TIMCLKEN1       : in     vl_logic;
        TIMCLKEN2       : in     vl_logic;
        ECOREVNUM       : in     vl_logic_vector(3 downto 0);
        PRDATA          : out    vl_logic_vector(31 downto 0);
        TIMINT1         : out    vl_logic;
        TIMINT2         : out    vl_logic;
        TIMINTC         : out    vl_logic
    );
end cmsdk_apb_dualtimers;
